(1) Field of the Invention
This invention relates generally to the field of read only memory (ROM) fabrication, and more particularly, to a ROM coding process during ROM manufacturing.
(2) Description of the Prior Art
ROM devices are standard components of modern computer and electronic systems. A ROM cell comprises an array of metal oxide semiconductor field effect transistors (MOSFETs) arranged in columns and rows. These MOSFETs are either normally on or normally off to represent a function code of the ROM. The alternative on/off operation of these devices states of the MOSFETs is adopted to use for storage of data, which remains in the device when the external power supply is off.
At the intersection of horizontal conductive lines in the array are commonly referred as "wordline", while the vertical conductive lines in the array are commonly referred as "bitline". Referring now more particularly to FIG. 1, there is shown a example circuit diagram representation of a typical ROM array comprising two bitlines BL.sub.1, BL.sub.2 and three wordlines WL.sub.1, WL.sub.2, WL.sub.3 that are made of NMOSs. The enhancement mode transistor M.sub.11 which is represented address (11) is non-conductive when wordline WL.sub.1 is selected (that is WL.sub.1 low and WL.sub.2, WL.sub.3 high), therefore, the output of bitline BL.sub.1 is 0. On the other hand, the depletion mode transistor M.sub.12 is conductive when wordline WL.sub.1 is selected, therefore, the output of bitline BL.sub.2 is 1. That is, the outputs of BL.sub.1, BL.sub.2 is (0,1). Similarly, the outputs of BL.sub.1, BL.sub.2 is (1,0) when wordline WL.sub.2 is low (WL.sub.1, WL.sub.3 are high). Again, the outputs of BL.sub.1, BL.sub.2 would be (0,0) when wordline WL.sub.3 is low (WL.sub.1, WL.sub.2 are high). A set of (0,1), (1,0) and (0,0) codes are pre-stored in the ROM array as shown in FIG. 1. The conductive status of the transistors determine the functions of a specific ROM array. These codes are placed in the semiconductor substrate via code implanting to provide predefined binary data of the ROMs.
Conventionally, the code implantation is performed at a very early stage because of process limitation. Since the ions (impurities) cannot penetrate thicker layers, code implantation is performed before the dielectric layer is formed. Subsequent process steps such as dielectric layer and metal layer deposition, annealing, and passivation layer deposition are still needed to complete the ROM manufacture. Therefore, long turn around time is required and is not suitable for flexible business competitions.
There are many ways to deal with this problem with later stage code implanting. U.S. Pat. No. 5,429,974 to Hsue et al. of United Microelectronics Corporation, Taiwan (the entire disclosure of which is herein incorporated by reference) provides a code implanting process after final passivation layer is formed. However, thinner final passivation layer is required for this approach that may degrade the ROM performance. Besides, post-implant activating step may damage the metal layer.
This invention reveals an improved ROM coding process to eliminate above mentioned problems. Neutron irradiation is described in the article entitled "Phosphorus doping silicon by means of neutron irradiation" by Hass et al., IEEE Transactions on Electron Devices, Vol. ED-23, No. 8, August 1976, pp. 803-805, which is fully incorporated by reference.